1. Field of the Invention
The present invention relates to data processing apparatuses (microprocessors, image processors, multimedia processors, IP cores, personal computers, network servers, mobile devices, game machines, PDAs (personal digital/data assistants), and the like) provided with an electronic circuit portion, and to data control circuits for use therein. More particularly, the present invention relates to a technique used therein for saving/restoring data.
2. Description of Related Art
Conventionally, temporarily stored data such as register data of an electronic circuit portion of a data processing apparatus is lost at shutdown, and, even after the power comes back on, it is impossible to restore the lost data to the original state. As a result, if an unintended power shutdown such as a power failure occurs, the conventional data processing apparatus suffers damage such as loss of data that is being worked on.
In addition, for a data processing apparatus such as a personal computer that needs software control, it is necessary to reload software when the power is turned on again. This makes it time-consuming to turn the power on/off (to start up the hardware), putting an unnecessary stress on a user. It is for this reason that the conventional data processing apparatus does not allow power to the electronic circuit portion to be easily shut down even when the electronic circuit portion is on standby. This undesirably increases wasteful power consumption.
Examples of a conventional technology related to what has been described thus far are seen in JP-A-S58-169218, JP-A-H4-107725, JP-A-2004-186874, JP-A-H10-78836, and JP-A-H3-163617 (hereinafter referred to as “Patent Documents 1 to 5” respectively).
Patent Document 1 discloses a power shutdown/restoration method by which, in a data processing apparatus storing a running state of a program that is being executed at the time of power off, such that continued execution of the program is made possible when power is restored (that is, an apparatus that can retain the program by means of battery or the like even if a power shutdown occurs), the data processing apparatus being provided with off-state detecting means for detecting that the power is turned off; a plurality of stack areas that store program running states during power off; and judging means for judging whether or not a running program stored in the stack areas is a power shutdown program that operates during power off, when the power is in a shutdown state, the program running states are sequentially stored in the plurality of stack areas; when power is restored, the program running states are sequentially read until a program other than the power shutdown program is read.
Patent Document 2 discloses a data saving/restoring method that restores data as follows. Judgment is made at regular intervals as to whether each area of a buffer memory satisfies a saving condition, and the data stored in the area that satisfies the saving condition is saved to a magnetic disk device. If a trouble occurs in the buffer memory, invalid area determining means differentiates between the area to which valid data is saved and the area to which invalid data is saved, such that the area to which the valid data is saved is restored by using the data saved to the magnetic disk device, and the area to which the invalid data is saved is restored based on the update history information.
Patent Document 3, which the applicant of the present invention once filed, discloses and proposes a data retaining apparatus provided with: a data retaining circuit that retains data, at the time of latching of data, by connecting first and second inverter circuits in a loop; and a non-volatile storage device that stores, at the time of writing of data, with one end thereof connected to an input node of the first inverter circuit, a non-volatile state corresponding to data existing in the data retaining circuit, and that releases, at the time of restoration of data, an electrical charge corresponding to the stored non-volatile state at the input node of the first inverter circuit, the electrical charge causing a voltage that is higher or lower than a threshold voltage of the first inverter circuit to appear at the input node of the first inverter circuit, by connecting the one end thereof to the input node of the first inverter circuit and receiving a read signal at the other end thereof. The data retaining circuit has a loop connecting/disconnecting gate inserted between a non-volatile storage device connection node at which the input node of the first inverter circuit and the one end of the non-volatile storage device are connected together and an output node of the second inverter circuit, the loop connecting/disconnecting gate being so controlled, at the time of latching and writing of data, as to be in a connected state, and so controlled, at the time of restoration of data, as to be in a disconnected state during the reception of the read signal and to be shifted in a connected state after a predetermined length of time elapses.
Patent Document 4 discloses and proposes a data processing apparatus for executing an instruction, the processing apparatus provided with: an element including a sequential circuit composed of a plurality of combinatorial logic circuits and a plurality of storage devices to be combined with the plurality of combinatorial logic circuits into a sequential circuit; a memory for saving; a saving/restoring circuit that reads a plurality of internal data stored in the plurality of storage devices and saves the plurality of internal data thus read to the memory for saving, and that reads the plurality of internal data thus saved from the memory for saving and restores the plurality of internal data thus read to the plurality of storage devices; and a power supply switching circuit that switches a source voltage to be fed to the processing apparatus, such that, after the plurality of internal data is saved by the saving/restoring circuit, a source voltage for a standby state is fed to the processing apparatus, and, before the plurality of internal data saved by the saving/restoring circuit is restored, a source voltage for normal operation is fed to the processing apparatus.
Patent Document 5 discloses and proposes a warm boot method for a program in a computer system including a central processing unit having at least a main memory, and an external storage device as needed. In this method, a power-failure interrupt indicating a power shutdown occurs shortly before the power to the computer system is shut down. When the power-failure interrupt occurs, the current states of a register and its peripheral integrated circuit of the central processing unit are saved to a specific address of the main memory, a flag indicating a power failure is set, and the process is on standby until power to the computer system is shut down. Upon shutdown of the power to the computer system, the power to the main memory is switched from a power source to a battery for backup. Upon power-on of the computer system, the power to the main memory is switched from the battery to the power source. At this point, if the flag indicating a power failure is set, the states of the register and its peripheral integrated circuit, the states saved at the occurrence of the power-failure interrupt, are restored to the original states, and the flag indicating a power failure is reset; if the flag indicating a power failure is not set, a control program and a processing program are loaded from the external storage device.
Certainly, with the conventional technologies disclosed in Patent Documents 1 to 5, it is possible to save/restore or retain data of an electronic circuit portion.
However, with the conventional technology disclosed in Patent Document 1, there is a need to provide, in addition to a main power source, a sub power source such as an uninterruptible power supply (UPS) or a battery backup. This undesirably increases the size and cost of the data processing apparatus.
With the technology disclosed in Patent Document 2, it is necessary to perform data backup operation during normal operation. This results in a considerable degradation in performance of the data processing apparatus. In addition, a decreased frequency of data backup disadvantageously increases the amount of data loss.
The conventional technology disclosed in Patent Document 3 simply aims at making it possible for the register used in the data storage circuit provided in the electronic circuit to retain data without power supply, but not at saving/restoring data.
The conventional technology disclosed in Patent Document 4 simply aims at reducing standby leakage current and hence power consumption by switching the source voltage before and after data saving, and does not suggest saving/restoration of data at the time of a power shutdown.
The technology disclosed in Patent Document 5 simply aims at saving/restoring the states of the register and its peripheral integrated circuit of the central processing unit by using a program executed on the central processing unit. This necessitates reloading of a restoration program after each restoration of data, making it time-consuming to turn the power on/off (to start up the hardware). Moreover, giving a data saving/restoring function to an existing system requires making changes in the program because otherwise compatibility of the program cannot maintained. Furthermore, data saving/restoring processing itself is time-consuming if it is handled by software.